The present invention relates in general to methods of fabrication and semiconductor structures, more particularly, to Field-Effect Transistor (FET) structures in metal gate technology having an electrically conductive oxygen barrier layer and most particularly, to FET structures in high dielectric constant (high K), metal gate technology having an electrically conductive oxygen barrier layer.
In the field of semiconductor devices, it is well known to form FETs having a gate, source and drain. Typically, the gate is formed by depositing a layer of silicon dioxide (SiO2) or silicon oxynitride (SiON), constituting a gate insulator layer, upon a silicon substrate and then depositing a poly-crystalline silicon (‘polysilicon’) layer, constituting a gate electrode layer, upon the gate insulator layer. The gate electrode layer, and optionally the gate insulator layer, is then etched to form an appropriately shaped gate.
Silicon dioxide and silicon oxynitride as a gate oxide and polysilicon as the gate electrode have been the standard materials for FETs. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric had to decrease steadily as well, to maintain good electrostatic control over the FET channel. However, with the thinning of the silicon dioxide comes the problem of leakage currents due to tunneling through the silicon dioxide.
To further reduce FET size, advanced technology processes use high-K dielectric materials for the gate dielectric layer along with metals other than polysilicon for the gate electrode. Such devices may be referred to as high-K/metal gate (HKMG) FETs. The high-K gate dielectric layer is generally deposited on a silicon substrate (with an optional interfacial layer present, for example SiO2 or SiON), and a metal gate electrode is formed on the high-K gate dielectric layer. Replacing the silicon dioxide dielectric with a high-K material reduces the leakage effects mentioned above, while improving electrostatic control over the channel.